1. Field of the Invention
The present invention relates to known good integrated circuit semiconductor devices in general, and more specifically to improved known good die (KGD) integrated circuit semiconductor devices having metallurgical test only contacts, and metallurgical contacts for providing connections to an end use device. This invention may optionally utilize wire bond technology, flip-chip controlled collapse chip connect technology, here in after C4, solder ball connections and ball grid array technologies.
2. The Prior Art
The description of known good die (KGD) has been described as the equivalent quality and reliability of the comparable packaged part. In essence a “die” is really a chip, but it is only referred to in this way when discussing physical parameters and manufacturing issues. KGD has also been defined as testing beyond conventional wafer probing. As methods for KGD assurance testing have improved, the art has and will continue to seek even better KGD devices. The testing for KGD should succeed as closely as possible to providing evaluation of die performance life span. In production of an improved KGD, not only electrical characteristics of the integrated circuit device, but also mechanical characteristics should be considered. Usually mechanical stresses on the integrated circuit device are produced by thermal stresses and may be taken into account when the integrated circuit device is being tested to determine if it qualifies as a KGD.
If an integrated circuit die, or integrated circuit device is defective prior to incorporation into an end use device such as a multi chip module (MCM) or other device, the result is expensive. The end use device will have to be either scrapped entirely, or reworked by substituting a good integrated circuit at a considerable expense. When many chips or dies are used in a multi chip module, the probability of a bad module increases dramatically as the number of dies increases. In prior art KGD testing of devices where there is no testing for electrical and thermal stress, the probability of a bad die or integrated circuit device is significant when MCM devices with a large number of dies are being made. For this reason, testing for the KGD integrated circuit should be as complete as possible and should address the problem of thermal stress and mechanical stresses as well as electrical problems. When the integrated circuit is installed in the end use device, confidence in its KGD qualification should be as high as possible.
It is known in the art to test integrated circuits having ball-type contacts (control collapse chip connection (C4)) contacts where the die is pressed or forced into a test fixture. The C4 balls are forced into contact with fixture surfaces or edges, which provide contact. Next, the die is tested electrically. However, this approach to limited KGD testing does not provide for a metallurgical bond between the die and the test fixture, and by forcing the die into a position, does not permit the die to naturally respond to conditions of thermal stress. Therefore, force holding of a die in a fixture does not provide the most complete KGD performance life span test. This testing also causes contact between a test fixture and solder balls such as C4 connections, which leaves the balls in a less than pristine condition. Contact with the test fixture can distort the balls, cause scratches, or otherwise change their characteristics which may ultimately effect solderability. The failure to maintain contacts in a pristine condition is a serious problem with this force-contact testing.
Complete burn-in testing is known in the art as a simulated life stress to assure survival of a packaged part. A certain percentage will fail early in their life. The burn-in test involves a temperature and electrical stress to eliminate the weak parts. The complete burn-in testing, however, has been done only at a packaged part level (die/complete device level), not at a KGD, wafer or other lower level prior to incorporation into an end use packaged part device. A KGD test should approach as closely as possible a complete burn-in test of the packaged part, but this is not possible because the packaging step includes untested connections to the KGD.
In prior art devices for testing dies, there has been no die developed which is capable of both KGD test procedures on either wire bond pads or solder ball array contacts, and then use of the remaining set of contacts for connection to an end use device. Therefore, the prior art does not permit manufacture of dies which can be used for either solder ball array connection or wire bond pad connection to an end use device after known good integrated circuit or KGD testing on the alternate set of contacts.
U.S. Pat. No. 5,367,763 to Lam shows a chip or die having solder interconnect pads which are for connection to an end use device or package. Around the periphery of the die are bond pads which are not initially connected to the interconnect pads when the die is first made. Testing is conducted by connecting the interconnect pads to the peripheral bond pads and the peripheral bond pads to test device terminals by a test by a test in a tape by a technique known as tape-automated-bonding. After testing, the leads between the peripheral bond pads and the test device are severed. Connection to an end use device is then made from the interconnect pad through a portion of the test lead with a solder ball or known flip-chip techniques.
It is known in the art to construct dies which are designed for use of a wire bond type pads to test the chip, and then use of tape-automated-bonding (TAB) to install the chip on an end use device. It is also known to use tape automated bonds (TAB) as a test array where after testing, the TAB contacts are severed. The art also has examples of using one set of contacts for testing, wherein the test contacts are subsequently removed from the die prior to installation of the die on an end use device.
One type of electrical and mechanical connection of an integrated circuit chip (die) to a package is called “flip-chip” or “controlled collapse chip connection” (C4) and is described in U.S. Pat. No. 3,401,126, to Lewis F. Miller, et al., and U.S. Pat. No. 3,429,040 to Lewis F. Miller. C4 involves forming solder balls on the surface of the chip that connect signal terminals of the chip with corresponding connections on the package, where the solder balls provide both electrical contact and mechanical support between the chip and the end use device. A disadvantage and difficulty with known C4 interconnections is that they do not allow testing prior to committing the chip to the end use device, other than wafer probe testing which does not allow testing with all the signal terminals metallurgically connected, or more complete KGD testing which can be performed with a soldered bond pad connection. Still further, wafer probe testing of the C4 solder balls undesirably disturbs their pristine condition because of the undesirable probe contact.
U.S. Pat. No. 5,517,127 to Bergeron et al., hereby incorporated by reference, shows the use of controlled collapse chip connection (C4) type solder ball connections in combination with wire bond pads. The C4 technology is used only for non-stress KGD testing the die prior to final connection to an end use device using wire bond technology. The solder balls are located away from the neutral point and will be highly stressed. The reference to C4 therefore does not teach that the connections are laid out and designed for thermal and mechanical stress. Not all C4 contacts are designed for thermal stress and Bergeron et al. is a good example. These C4 connections are not in an array designed for stress tolerance which can withstand thermal stress because they are limited in number and placed away from the chip center.
There is no provision in Bergeron for use of wire bond technology to test a die which will be optionally connected to a an end use device by solder ball C4 array. The test electrical connectors are placed entirely in a plane above the wire bond pads and are not required to be removed after testing of the die. The solder ball test balls protrude above the level of the wire bond pad which allows testing between the die and a test device without affecting the surface of the wire bond pad. The solder balls and the wire bond pads are not on the same planar surface. In another aspect, the disclosure provides that the wire bond die has a wire bond pad disposed at an upper surface of the die. This procedure eliminates probe testing on the wire bond pad and gives metallurgical ball test connections. Wafer dicing may be done before or after testing and there is no need for removal of the added test elements. The subsequent electrical connection, however, is always by wire bond connection.
The testing disclosed in Bergeron cannot withstand more than a few thermal cycles because the stresses will cause breaking of the solder metallurgical joints. The Bergeron type of connections may provide for only 40 joints. In contrast, some stress tolerant solder ball array contacts have up to or more than 400 joints, are located close to the chip center and may be designed for specific thermal stress and mechanical characteristics.
It is also known in the prior art to use redundant C4 connections where one centrally located set is used for the final connection to the end use device, and the other set is used for testing. However, this is not a reliable KGD performance life span alternative, because the C4 array used in testing the final end product has to be mechanically strong as well as electrically correct. The test set of (C)4 connections cannot be used to stress tolerant test an integrated circuit because it will fail within ten cycles because of lack of mechanical strength available for the C4 test connections which are necessarily at the periphery. This is because the stresses increase as on moves out from the center of a C4 array. This heretofore known C4 testing has been used only for electrical testing. Mere use of C4 peripheral balls in place of wire bond pads will not work for KGD testing of a centrally located flip-chip C4 array. The reason is that if only C4 ball contacts are used around the periphery of the chip, instead of pads, these C4 ball contacts will experience very high thermal stress, because they are away from the center contact. Such a peripheral array of balls will quickly deteriorate and break under a few cycles of thermal stress.
In addition to the above discussed prior art, it should be noted that wafer level testing of dies is well known. This type of testing, however, uses probe cards which upon contact with bond pads or solder balls may cause damage to the pads or halls which will effect later bonding to a module or packaging. This type of testing does not provide for a good metallurgical contact and cannot provide a KGD test where thermal and mechanical stress are accounted for at the die, integrated circuit or wafer level.